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| EtronTech Features Clock rate: 200/183/166/143/125/100 MHz Fully synchronous operation Internal pipelined architecture Four internal banks (512K x 32bit x 4bank) Programmable Mode - CAS# Latency: 2 or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst-Read-Single-Write * Burst stop function * Individual byte controlled by DQM0-3 * Auto Refresh and Self Refresh * 4096 refresh cycles/64ms * Single +3.3V 0.3V power supply * Interface: LVTTL * Package: 400 x 875 mil, 86 Pin TSOP II, 0.50mm pin pitch Lead Free Package available * * * * * * EM638325 2M x 32 Synchronous DRAM (SDRAM) Preliminary (Rev 1.4 October/2005) Pin Assignment (Top View) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 /WE /CAS /RAS /CS NC BS0 BS1 A10/AP A0 A1 A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS Ordering Information Part Number Leaded / Lead Free Package EM638325TS-5/-5G EM638325TS-5.5/-5.5G EM638325TS-6/-6G EM638325TS-7/-7G EM638325TS-8/-8G EM638325TS-10/-10G 200MHz 183MHz 166MHz 143MHz 125MHz 100MHz TSOP II TSOP II TSOP II TSOP II TSOP II TSOP II Frequency Package Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. EtronTech Overview 2Mega x 32 SDRAM EM638325 The EM638325 SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It is internally configured as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 32 bit banks is organized as 2048 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The EM638325 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth. Block Diagram Col um n Row Decoder De co der 2048 X 256 X 32 CELL ARRAY (BANK #0) Sense Ampl ifier CL K DLL CL OCK B U FFER CON TRO L SI G N A L GEN ER A TO R Sense Row Decoder CK E Ampl ifier C S# R A S# C A S# W E# COMMAND D E C O D ER M OD E R EG I ST ER 2048 X 256 X 32 CELL ARRAY (BANK #1) Col um n De coder CO LU MN C OU N T ER A 10/A P Col um n Row Decoder De co der A0 A9 B S0 B S1 A D D R E SS B U FFER 2048 X 256 X 32 CELL ARRAY (BANK #2) Sense Ampl ifier R E F R E SH C O U N TER Sense DQ B U FFER D Q0 D Q31 Row Decoder Ampl ifier 2048 X 256 X 32 CELL ARRAY (BANK #3) Col um n De co der D QM 0~3 Preliminary 2 Rev 1.4 Oct. 2005 EtronTech Pin Descriptions 2Mega x 32 SDRAM EM638325 Table 1. Pin Details of EM638325 Symbol Type Description CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes low synchronously with clock(set-up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except after the device enters Power Down and Self Refresh modes, where CKE becomes asynchronous until exiting the same mode. The input buffers, including CLK, are disabled during Power Down and Self Refresh modes, providing low standby power. Input Bank Select: BS0 and BS1 defines to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. BS is also used to program the 11th bit of the Mode and Special Mode registers. CKE BS0, BS1 A0-A10 Input Address Inputs: A0-A10 are sampled during the BankActivate command (row address A0A10) and Read/Write command (column address A0-A7 with A10 defining Auto Precharge) to select one location out of the 256K available in the respective bank. During a Precharge command, A10 is sampled to determine if all banks are to be precharged (A10 = HIGH). The address inputs also provide the op-code during a Mode Register Set or Special Mode Register Set command. CS# Input Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external bank selection on systems with multiple banks. It is considered part of the command code. Input Row Address Strobe: The RAS# signal defines the operation commands in conjunction with the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate command or the Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH," the BankActivate command is selected and the bank designated by BS is turned on to the active state. When the WE# is asserted "LOW," the Precharge command is selected and the bank designated by BS is switched to the idle state after the precharge operation. Input Column Address Strobe: The CAS# signal conjunction with the RAS# and WE# signals and When RAS# is held "HIGH" and CS# is asserted asserting CAS# "LOW." Then, the Read or Write "LOW" or "HIGH." defines the operation commands in is latched at the positive edges of CLK. "LOW," the column access is started by command is selected by asserting WE# RAS# CAS# WE# Input Write Enable: The WE# signal defines the operation commands in conjunction with the RAS# and CAS# signals and is latched at the positive edges of CLK. The WE# input is used to select the BankActivate or Precharge command and Read or Write command. DQM0 - Input Data Input/Output Mask: DQM0-DQM3 are byte specific, nonpersistent I/O buffer controls. DQM3 The I/O buffers are placed in a high-z state when DQM is sampled HIGH. Input data is masked when DQM is sampled HIGH during a write cycle. Output data is masked (twoclock latency) when DQM is sampled HIGH during a read cycle. DQM3 masks DQ31DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8, and DQM0 masks DQ7-DQ0. DQ0- Input/ Data I/O: The DQ0-31 input and output data are synchronized with the positive edges of DQ31 Output CLK. The I/Os are byte-maskable during Reads and Writes. Preliminary 3 Rev 1.4 Oct. 2005 EtronTech NC VDDQ VSSQ VDD VSS Supply Power Supply: +3.3V0.3V Supply Ground 2Mega x 32 SDRAM EM638325 No Connect: These pins should be left unconnected. Supply DQ Power: Provide isolated power to DQs for improved noise immunity. Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. Preliminary 4 Rev 1.4 Oct. 2005 EtronTech Operation Mode 2Mega x 32 SDRAM EM638325 Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows the truth table for the operation commands. Table 2. Truth Table (Note (1), (2) ) Command BankActivate BankPrecharge PrechargeAll Write Write and AutoPrecharge Read Read and Autoprecharge Mode Register Set No-Operation Burst Stop Device Deselect AutoRefresh SelfRefresh Entry SelfRefresh Exit State Idle(3) Any Any Active(3) Active(3) Active(3) Active(3) Idle Any Active(4) Any Idle Idle Idle (SelfRefresh) CKEn-1 CKEn DQM(6) BS0,1 A10 H H H H H H H H H H H H H L H H L L H X X X X X X X X X X X H L H L L H H X X X X X X X X X X X X X X X X X X X L X X X X X X X X X X X V V X V V V V L H L H L H A9-0 X X Column address (A0 ~ A7) Column address (A0 ~ A7) CS# RAS# CAS# WE# L L L L L L L L L L L H H H H L H H X L L X H X X H X X H X H H H L L L L L H H X L L X H X X H X X H X H L L L L H H L H L X H H X H X X H X X H X X Row address OP code X X X X X X X X X X X X X X X X X X X X X X L L H L L H L X H L X H L X Clock Suspend Mode Entry Power Down Mode Entry Active Any(5) Active Any (PowerDown) Clock Suspend Mode Exit Power Down Mode Exit Data Write/Output Enable Data Mask/Output Disable Active Active H X H X X X X X X Note: 1. V = Valid, X = Don't care, L = Logic low, H = Logic high 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BS signal. 4. Device state is 1, 2, 4, 8, and full page burst operation. 5. Power Down Mode can not enter in the burst operation. When this command is asserted in the burst cycle, device state is clock suspend mode. 6. DQM0-3 Preliminary 5 Rev 1.4 Oct. 2005 EtronTech Commands 1 2Mega x 32 SDRAM EM638325 BankActivate (RAS# = "L", CAS# = "H", WE# = "H", BS = Bank, A0-A10 = Row Address) The BankActivate command activates the idle bank designated by the BS0,1 (Bank Select) signal. By latching the row address on A0 to A10 at the time of this command, the selected row access is initiated. The read or write operation in the same bank can occur after a time delay of tRCD(min.) from the time of bank activation. A subsequent BankActivate command to a different row in the same bank can only be issued after the previous active row has been precharged (refer to the following figure). The minimum time interval between successive BankActivate commands to the same bank is defined by tRC(min.). The SDRAM has four internal banks on the same chip and shares part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back activation of the four banks. tRRD(min.) specifies the minimum time required between activating different banks. After this command is used, the Write command and the Block Write command perform the no mask write operation. T0 T1 T2 T3 .............. Bank A Row Addr. RAS# - CAS# delay (tRCD) Bank A Col Addr. .............. Bank B Row Addr. RAS# - RAS# delay time (tRRD) R/W A with AutoPrecharge Tn+3 Tn+4 Tn+5 Tn+6 CLK ADDRESS Bank A Row Addr. COM MAND Bank A Activate NOP NOP .............. Bank B Activate NOP NOP Bank A Activate RAS# Cycle time (tRC) AutoPrecharge Begin : "H" or "L" BankActivate Command Cycle (Burst Length = n, CAS# Latency = 3) 2 BankPrecharge command (RAS# = "L", CAS# = "H", WE# = "L", BS = Bank, A10 = "L", A0-A9 = Don't care) The BankPrecharge command precharges the bank disignated by BS0,1 signal. The precharged bank is switched from the active state to the idle state. This command can be asserted anytime after tRAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any bank can be active is specified by tRAS(max.). Therefore, the precharge function must be performed in any active bank within tRAS(max.). At the end of precharge, the precharged bank is still in the idle state and is ready to be activated again. PrechargeAll command (RAS# = "L", CAS# = "H", WE# = "L", BS = Don't care, A10 = "H", A0-A9 = Don't care) The PrechargeAll command precharges all the four banks simultaneously and can be issued even if all banks are not in the active state. All banks are then switched to the idle state. Read command (RAS# = "H", CAS# = "L", WE# = "H", BS = Bank, A10 = "L", A0-A7 = Column Address) The Read command is used to read a burst of data on consecutive clock cycles from an active row in an active bank. The bank must be active for at least tRCD(min.) before the Read command is issued. During read bursts, the valid data-out element from the starting column address will be available following the CAS# latency after the issue of the Read command. Each subsequent dataout element will be valid by the next positive clock edge (refer to the following figure). The DQs go into high-impedance at the end of the burst unless other command is initiated. The burst length, burst sequence, and CAS# latency are determined by the mode register which is already programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). 3 4 Preliminary 6 Rev 1.4 Oct. 2005 EtronTech T0 T1 T2 T3 CL K COMMAND READ A NOP NOP NOP 2Mega x 32 SDRAM T4 T5 T6 EM638325 T7 T8 NOP NOP NOP NOP NOP CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 Burst Read Operation(Burst Length = 4, CAS# Latency = 2, 3) The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e. DQM latency is two clocks for output buffers). A read burst without the auto precharge function may be interrupted by a subsequent Read or Write command to the same bank or the other active bank before the end of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank too. The interrupt coming from the Read command can occur on any clock cycle following a previous Read command (refer to the following figure). T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A READ B NOP NOP NOP NOP NOP NOP NOP CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3) The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from a Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a single cycle with high-impedance on the DQ pins must occur between the last read data and the Write command (refer to the following three figures). If the data output of the burst read occurs at the second clock of the burst write, the DQMs must be asserted (HIGH) at least one clock prior to the Write command to avoid internal bus contention. Preliminary 7 Rev 1.4 Oct. 2005 EtronTech T0 T1 T2 T3 CLK DQM 2Mega x 32 SDRAM T4 T5 T6 EM638325 T7 T8 COM MAND NOP READ A NOP NOP NOP NOP WRITE B NOP NOP DQ's DOUT A0 Must be Hi-Z before the Write Command DI NB 0 DINB1 DI NB 2 : "H" or "L" Read to Write Interval (Burst Length 4, CAS# Latency = 3) T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 1 Clk Interval DQM COMMAND NOP NOP BANKA ACTIVATE NOP READ A WRITE A NOP NOP NOP CAS# latency=2 tCK2, DQ's DIN A0 DIN A1 DIN A2 DIN A3 : "H" or "L" Read to Write Interval (Burst Length 4, CAS# Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK DQM COMMAND CAS# latency=2 tCK2, DQ's NOP NOP READ A NOP NOP WRITE B NOP NOP NOP DIN B0 DIN B1 DIN B2 DIN B3 : "H" or "L" Read to Write Interval (Burst Length 4, CAS# Latency = 2) A read burst without the auto precharge function may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank. The following figure shows the optimum time that BankPrecharge/ PrechargeAll command is issued in different CAS# latency. Preliminary 8 Rev 1.4 Oct. 2005 EtronTech T0 CL K Bank, Col A T1 T2 T3 ADDRESS 2Mega x 32 SDRAM T4 T5 T6 EM638325 T7 T8 Bank(s) Bank, Row tRP COMMAND READ A NOP NOP NOP Precharge NOP NOP Activate NOP CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 Read to Precharge (CAS# Latency = 2, 3) 5 Read and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "H", BS = Bank, A10 = "H", A0-A7 = Column Address) The Read and AutoPrecharge command automatically performs the precharge operation after the read operation. Once this command is given, any subsequent command cannot occur within a time delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in this command and the auto precharge function is ignored. Write command (RAS# = "H", CAS# = "L", WE# = "L", BS = Bank, A10 = "L", A0-A7 = Column Address) The Write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank. The bank must be active for at least tRCD(min.) before the Write command is issued. During write bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data elements will be registered on each successive positive clock edge (refer to the following figure). The DQs remain with high-impedance at the end of the burst unless another command is initiated. The burst length and burst sequence are determined by the mode register, which is already programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 6 COM MAND NOP WRITE A NOP NOP NOP NOP NOP NOP NOP DQ0 - DQ3 DIN A0 DIN A1 DIN A2 DIN A3 don't care The first data element and the write are registered on the same clock edge. Extra data is masked. Burst Write Operation (Burst Length = 4, CAS# Latency = 1, 2, 3) A write burst without the AutoPrecharge function may be interrupted by a subsequent Write, BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt coming from Write command can occur on any clock cycle following the previous Write command (refer to the following figure). Preliminary 9 Rev 1.4 Oct. 2005 EtronTech T0 CLK T1 T2 T3 COMMAND NOP WRITE A WRITE B NOP 1 Clk Interval DQ's DIN A0 DIN B0 DIN B1 2Mega x 32 SDRAM T4 T5 T6 EM638325 T7 T8 NOP NOP NOP NOP NOP DIN B2 DIN B3 Write Interrupted by a Write (Burst Length = 4, CAS# Latency = 1, 2, 3) The Read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid data contention, input data must be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to the following figure). Once the Read command is registered, the data inputs will be ignored and writes will not be executed. T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 COMMAND NOP WRITE A READ B NOP NOP NOP NOP NOP NOP CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's DIN A0 don't care DOUT B0 DOUT B1 DOUT B2 DOUT B3 DIN A0 don't care don't care DOUT B0 DOUT B1 DOUT B2 DOUT B3 Input data for the write is masked. Input data must be removed from the DQ's at least one clock cycle before the Read data appears on the outputs to avoid data contention. Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3) The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function should be issued m cycles after the clock edge in which the last data-in element is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM signals must be used to mask input data, starting with the clock edge following the last data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is entered (refer to the following figure). T0 CLK T1 T2 T3 T4 T5 T6 DQM tRP COMM AND WRITE NOP Precharge NOP NOP Activate NOP ADDRESS BA NK COL n DIN n DIN n+1 BANK (S) tWR ROW DQ : don't care Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2. Write to Precharge Preliminary 10 Rev 1.4 Oct. 2005 EtronTech 7 2Mega x 32 SDRAM EM638325 Write and AutoPrecharge command (refer to the following figure) (RAS# = "H", CAS# = "L", WE# = "L", BS = Bank, A10 = "H", A0-A7 = Column Address) The Write and AutoPrecharge command performs the precharge operation automatically after the write operation. Once this command is given, any subsequent command can not occur within a time delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is performed in this command and the auto precharge function is ignored. T0 CLK Bank A Activate Write A AutoPrecharge T1 T2 T3 T4 T5 T6 T7 T8 COMMAND NOP NOP NOP NOP NOP NOP NOP tDAL CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's DIN A0 DIN A1 * tDAL DIN A0 DIN A1 tDAL= tWR + tRP * * Begin AutoPrecharge Bank can be reactivated at completion of tDAL Burst Write with Auto-Precharge (Burst Length = 2, CAS# Latency = 2, 3) 8 Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", BS0,1 and A10-A0 = Register Data) The mode register stores the data for controlling the various operating modes of SDRAM. The Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst Length in the Mode register to make SDRAM useful for a variety of different applications. The default values of the Mode Register after power-up are undefined; therefore this command must be issued at the power-up sequence. The state of pins BS0,1 and A10~A0 in the same cycle is the data written to the mode register. One clock cycle is required to complete the write in the mode register (refer to the following figure). The contents of the mode register can be changed using the same command and the clock cycle requirements during operation as long as all banks are in the idle state. Preliminary 11 Rev 1.4 Oct. 2005 EtronTech T0 CLK tCK2 CKE T1 T2 T3 T4 2Mega x 32 SDRAM T5 T6 T7 T8 T9 EM638325 T10 Clock min. CS# RAS# CAS# WE# Address Key ADDR. DQM tRP DQ Hi-Z PrechargeAll Mode Register Set Command Any Command Mode Register Set Cycle (CAS# Latency = 2, 3) The mode register is divided into various fields depending on functionality. Address BS0,1 A10/AP Function RFU* RFU* A9 WBL A8 A7 A6 A5 A4 A3 BT A2 A1 A0 Test Mode CAS Latency Burst Length *Note: RFU (Reserved for future use) should stay "0" during MRS cycle. * Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4, 8, or full page. A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Length 1 2 4 8 Reserved Reserved Reserved Full Page Preliminary 12 Rev 1.4 Oct. 2005 EtronTech A3 0 Burst Type Sequential 2Mega x 32 SDRAM EM638325 * Burst Type Field (A3) The Burst Type can be one of two modes, Interleave Mode or Sequential Mode. 1 Interleave --- Addressing Sequence of Sequential Mode An internal column address is performed by increasing the address from the column address which is input to the device. The internal column address is varied by the Burst Length as shown in the following table. When the value of column address, (n + m), in the table is larger than 255, only the least significant 8 bits are effective. Data n Column Address 0 n 1 n+1 2 n+2 3 n+3 4 n+4 5 n+5 6 n+6 7 n+7 - 255 N+25 5 256 n 257 n+1 - 2 words: Burst Length 4 words: 8 words: Full Page: Column address is repeated until terminated. --- Addressing Sequence of Interleave Mode A column access is started in the input column address and is performed by inverting the address bits in the sequence shown in the following table. Data n Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 A7 A7 A7 A7 A7 A7 A7 A7 A6 A6 A6 A6 A6 A6 A6 A6 A5 A5 A5 A5 A5 A5 A5 A5 Column Address A4 A3 A4 A4 A4 A4 A4 A4 A4 A3 A3 A3 A3 A3 A3 A3 Burst Length A2 A2 A2 A2 A2# A2# A2# A2# A1 A1 A1# A1# A1 A1 A1# A1# A0 A0# A0 A0# A0 A0# A0 A0# 4 words 8 words * CAS# Latency Field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS# Latency depends on the frequency of CLK. The minimum whole value satisfying the following formula must be programmed into this field. tCAC(min) CAS# Latency X tCK A6 0 0 0 0 1 A5 0 0 1 1 X A4 0 1 0 1 X CAS# Latency Reserved Reserved 2 clocks 3 clocks Reserved Preliminary 13 Rev 1.4 Oct. 2005 EtronTech A8 0 A7 0 2Mega x 32 SDRAM EM638325 * Test Mode field (A8~A7) These two bits are used to enter the test mode and must be programmed to "00" in normal operation. Test Mode normal mode 0 1 Vendor Use Only 1 X Vendor Use Only * Write Burst Length (A9) This bit is used to select the burst write length. A9 0 1 9 Write Burst Length Burst Single Bit No-Operation command (RAS# = "H", CAS# = "H", WE# = "H") The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS# is Low). This prevents unwanted commands from being registered during idle or wait states. 10 Burst Stop command (RAS# = "H", CAS# = "H", WE# = "L") The Burst Stop command is used to terminate either fixed-length or full-page bursts. This command is only effective in a read/write burst without the auto precharge function. The terminated read burst ends after a delay equal to the CAS# latency (refer to the following figure). The termination of a write burst is shown in the following figure. T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A NOP NOP NOP Burst Stop NOP NOP NOP NOP The burst ends after a delay equal to the CAS# latency. CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 Termination of a Burst Read Operation (Burst Length 4, CAS# Latency = 2, 3) T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 COMMAND NOP WRITE A NOP NOP Burst Stop NOP NOP NOP NOP CAS# latency= 2, 3 DQ's DIN A0 DIN A1 DIN A2 don't care Input data for the Write is masked. Termination of a Burst Write Operation (Burst Length = X, CAS# Latency = 1, 2, 3) Preliminary 14 Rev 1.4 Oct. 2005 EtronTech 11 2Mega x 32 SDRAM EM638325 Device Deselect command (CS# = "H") The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar to the No Operation command. AutoRefresh command (RAS# = "L", CAS# = "L", WE# = "H",CKE = "H", BS0,1 = "Don`t care, A0-A10 = Don't care) The AutoRefresh command is used during normal operation of the SDRAM and is analogous to CAS#-before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh operation must be performed 4096 times within 64ms. The time required to complete the auto refresh operation is specified by tRC(min.). To provide the AutoRefresh command, all banks need to be in the idle state and the device must not be in power down mode (CKE is high in the previous cycle). This command must be followed by NOPs until the auto refresh operation is completed. The precharge time requirement, tRP(min), must be met before successive auto refresh operations are performed. SelfRefresh Entry command (RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A10 = Don't care) The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh mode for data retention and low power operation. Once the SelfRefresh command is registered, all the inputs to the SDRAM become "don't care" with the exception of CKE, which must remain LOW. The refresh addressing and timing is internally generated to reduce power consumption. The SDRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command). 12 13 14 SelfRefresh Exit command (CKE = "H", CS# = "H" or CKE = "H", RAS# = "H", CAS# = "H", WE# = "H") This command is used to exit from the SelfRefresh mode. Once this command is registered, NOP or Device Deselect commands must be issued for tRC(min.) because time is required for the completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are performed during normal operation, a burst of 4096 auto refresh cycles should be completed just prior to entering and just after exiting the SelfRefresh mode. 15 Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L") When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from the subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held intact while CLK is suspended. On the other hand, when all banks are in the idle state, this command performs entry into the PowerDown mode. All input and output buffers (except the CKE buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown state longer than the refresh period (64ms) since the command does not perform any refresh operations. Clock Suspend Mode Exit / PowerDown Mode Exit command When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active state. tPDE(min.) is required when the device exits from the PowerDown mode. Any subsequent commands can be issued after one clock cycle from the end of this command. Data Write / Output Enable, Data Mask / Output Disable command (DQM = "L", "H") During a write cycle, the DQM signal functions as a Data Mask and can control every word of the input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is also used for device selection, byte selection and bus control in a memory system. 16 17 Preliminary 15 Rev 1.4 Oct. 2005 EtronTech Absolute Maximum Rating Symbol VIN, VOUT VDD, VDDQ TOPR TSTG TSOLDER PD IOUT Item Input, Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current 2Mega x 32 SDRAM EM638325 Note 1 1 1 1 1 1 1 Leaded Package Lead Free Package Unit -1~4.6 - 1~4.6 0~70 - 55~150 240 1 50 260 V V C C C W mA Recommended D.C. Operating Conditions (Ta = 0~70C) Symbol VDD VDDQ VIH VIL Parameter Power Supply Voltage Power Supply Voltage(for I/O Buffer) LVTTL Input High Voltage LVTTL Input Low Voltage Min. 3.0 3.0 2.0 - 0.3 Typ. 3.3 3.3 Max. 3.6 3.6 VDDQ + 0.3 0.8 Unit V V V V Note 2 2 2 2 Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25C) Symbol CI CI/O Parameter Input Capacitance Input/Output Capacitance Min. Max. 4.5 6.5 Unit pF pF Note: These parameters are periodically sampled and are not 100% Preliminary 16 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Recommended D.C. Operating Conditions (VDD = 3.3V 0.3V, Ta = 0~70C) Description/Test condition Operating Current 1 bank tRC tRC(min), Outputs Open, Input operation signal one transition per one cycle Precharge Standby Current in power down mode tCK = 15ns, CKE VIL(max) Precharge Standby Current in power down mode tCK = , CKE VIL(max) Precharge Standby Current in non-power down mode tCK = 15ns, CS# VIH(min), CKE VIH Input signals are changed once during 30ns. Precharge Standby Current in non-power down mode tCK = , CLK VIL(max), CKE VIH Active Standby Current in power down mode CKE VIL(max), tCK = 15ns Active Standby Current in power down mode CKE & CLK VIL(max), tCK = Active Standby Current in non-power down mode CKE VIH(min), CS# VIH(min), tCK = 15ns Active Standby Current in non-power down mode CKE VIH(min), CLK VIL(max), tCK = Operating Current (Burst mode) tCK =tCK(min), Outputs Open, Multi-bank interleave Refresh Current tRC TrC(min) Self Refresh Current CKE 0.2V Symbol ICC1 - 5/5.5/6/7/8/10 Max. Unit Note 200/190/180/155/135/120 3 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS ICC4 ICC5 ICC6 3 3 25 15 5 5 40 30 225/215//200/180/150/130 260/240/220/210/190/180 2 mA 3 3 3 3 3, 4 3 Parameter IIL VOH VOL Description Input Leakage Current ( 0VVINVDD, All other pins not under test = 0V ) LVTTL Output "H" Level Voltage ( IOUT = -2mA ) LVTTL Output "L" Level Voltage ( IOUT = 2mA ) Min. - 1.5 2.4 Max. 1.5 0.4 Unit A V V Note Preliminary 17 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Electrical Characteristics and Recommended A.C. Operating Conditions (VDD = 3.3V 0.3V, Ta = 0~70C) (Note: 5, 6, 7, 8) Symbol A.C. Parameter - 5/5.5/6/7/8/10 Min. Max. Unit Note tRC tRRD tRCD tRP tRAS tCK2 tCK3 tAC2 tAC3 tOH tCH tCL tIS tIH tLZ tHZ2 tHZ3 tWR tCCD tMRS Row cycle time (same bank) Row activate to row activate delay (different banks) RAS# to CAS# delay (same bank) Precharge to refresh/row activate command (same bank) Row activate to precharge time (same bank) Clock cycle time CL* = 2 CL* = 3 Access time from CLK (positive edge) Data output hold time Clock high time Clock low time Data/Address/Control Input set-up time Data/Address/Control Input hold time Data output low impedance Data output high impedance Write recovery time CAS# to CAS# Delay time Mode Register Set cycle time CL* = 2 CL* = 3 CL* = 2 CL* = 3 55/55/60/70/80/100 10/11/12/14/16/20 18/18/18/21/24/30 15/16.5/18/21/24/30 35/38.5/42/49/56/70 -/-/10/10/ - / 5/5.5/6/7/8/10 -/-/6/6/-/4.5/5/5.5/5.5/6/6 2/2/2/2.5/2.5/2.5 2/2/2.5/3/3/3.5 2/2/2.5/3/3/3.5 1.5/1.5/1.5/1.75/2/2.5 1 1 -/-/6/6/-/4.5/5/5.5/5.5/6/6 2 2/1/1/1/1/1 2 CLK ns 100,000 9 9 9 9 9 9 9 10 10 10 10 9 8 * CL is CAS# Latency. Note: 1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. 2. All voltages are referenced to VSS. 3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during tCK. 4. These parameters depend on the output loading. Specified values are obtained with the output open. 5. Power-up sequence is described in Note 11. Preliminary 18 Rev 1.4 Oct. 2005 EtronTech 6. A.C. Test Conditions 2Mega x 32 SDRAM EM638325 LVTTL Interface Reference Level of Output Signals Output Load Input Signal Levels Transition Time (Rise and Fall) of Input Signals Reference Level of Input Signals 3.3V 1.4V / 1.4V Reference to the Under Output Load (B) 2.4V / 0.4V 1ns 1.4V 1.4V 50 1.2k Z0= 5 0 Output 30pF 87 0 Output 30pF LVTTL D.C. Test Load (A) LVTTL A.C. Test Load (B) 7. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a fixed slope (1 ns). 8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels. 9. If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter. 10. Assumed input rise and fall time tT ( tR & tF ) = 1 ns If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns should be added to the parameter. 11. Power up Sequence Power up must be performed in the following sequence. 1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state and both CKE = "H" and DQM = "H." The CLK signals must be started at the same time. 2) After power-up, a pause of 200 seconds minimum is required. Then, it is recommended that DQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance. 3) All banks must be precharged. 4) Mode Register Set command must be asserted to initialize the Mode register. 5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device. Preliminary 19 Rev 1.4 Oct. 2005 EtronTech Timing Waveforms 2Mega x 32 SDRAM EM638325 Figure 1. AC Parameters for Write Timing (Burst Length=4, CAS# Latency=2) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCH CKE tCL tIS tIS tIH tCK2 Begin AutoPrecharge Bank A Begin AutoPrecharge Bank B tIS CS# RAS# CAS# WE# BS0,1 tIS ADDR. RBx tIH CAx RBx CBx RAy CAy RAz RBy DQM tRCD Hi-Z tRC Ax0 Ax1 Ax2 Ax3 tDAL Bx0 Bx1 Bx2 tIS Bx3 Ay0 tIH Ay1 Ay2 tWR tRP Ay3 tRRD DQ Activate Write with Activate Write with Activate Command AutoPrecharge Command AutoPrecharge Command Bank A Command Bank B Command Bank A Bank A Bank B Write Command Bank A Precharge Activate Command Command Bank A Bank A Activate Command Bank B Preliminary 20 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 2. AC Parameters for Read Timing (Burst Length=2, CAS# Latency=2) T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 tCH tCL CKE tCK2 tIS Begin AutoPrecharge Bank B tIS CS# RAS# tIH tIH CAS# WE# BS0,1 tIH A10 RAx RBx RAy tIS A0-A11 RAx CAx RBx CBx RAy tRRD tRAS DQM Hi-Z DQ tRC tRCD tAC2 tLZ tAC2 Ax0 tHZ Ax1 Bx0 tRP Bx1 tOH Activate Command Bank A Read Command Bank A Activate Command Bank B Read with Auto Precharge Command Bank B Precharge Command Bank A tHZ Activate Command Bank A Preliminary 21 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 3. Auto Refresh (CBR) (Burst Length=4, CAS# Latency=2) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx CAx DQM tRP tRC tRC DQ Read Command Bank A Ax0 Ax1 Ax2 Ax3 PrechargeAll Command AutoRefresh Command AutoRefresh Command Activate Command Bank A Preliminary 22 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 4. Power on Sequence and Auto Refresh (CBR) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CL K tCK2 CKE High level is reauired Minimum of 2 Refresh Cycles are required CS# RAS# CAS# WE# BS0,1 A10 Address Key A0-A9 DQM tRP DQ Hi-Z tRC PrechargeALL Command Inputs must be stable for 200 s 1st AutoRefresh Command Mode Register Set Command 2nd Auto Refresh Command Any Command Preliminary 23 Rev 1.4 Oct. 2005 EtronTech Figure 5. Self Refresh Entry & Exit Cycle 2Mega x 32 SDRAM EM638325 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 CLK *Note 2 *Note 1 *Note 4 *Note 3 tRC(min) tSRX *Note 7 CKE tPDE *Note 5 *Note 6 tIS CS# RAS# *Note 8 *Note 8 CAS# BS0,1 A0-A9 WE# DQM DQ Hi-Z Hi-Z Self Refresh Enter SelfRefresh Exit AutoRefresh Note: To Enter SelfRefresh Mode 1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in SelfRefresh mode as long as CKE stays "low". 4. Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh. 5. 6. 7. 8. 9. To Exit SelfRefresh Mode System clock restart and be stable before returning CKE high. Enable CKE and CKE should be set high for minimum time of tSRX. CS# starts from high. Minimum tRC is required after CKE going high to complete SelfRefresh exit. 4096 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the system uses burst refresh. Preliminary 24 Rev 1.4 Oct. 2005 EtronTech Figure 6.1. 2Mega x 32 SDRAM EM638325 Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=1) T0 CLK T 1 T2 T3 T4 T5 T6 T 7 T8 T9 T10 T 11 T1 T13 T14 T15 T16 T17 T1 T19 T20 T21 T22 tCK1 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx CAx DQM tHZ DQ Hi-Z Ax3 Ax0 Ax1 Ax2 Activate Command Bank A Read Command Bank A Clock Suspend 1 Cycle Clock Suspend 2 Cycles Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock Preliminary 25 Rev 1.4 Oct. 2005 EtronTech Figure 6.2. 2Mega x 32 SDRAM EM638325 Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=2) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx CAx DQM tHZ DQHi-Z Ax0 Ax1 Ax2 Ax3 Activate Command Bank A Read Command Bank A Clock Suspend 1 Cycle Clock Suspend 2 Cycles Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock Preliminary 26 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 6.3. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=3) T0 CLK T 1 T 2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx CAx DQM tHZ DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Activate Command Bank A Read Command Bank A Clock Suspend Clock Suspend 1 Cycle 2 Cycles Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock Preliminary 27 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 7.1. Clock Suspension During Burst Write (Using CKE) (Burst Length = 4, CAS# Latency = 1) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx CAx DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 Activate Clock Suspend Command 1 Cycle Bank A Write Command Bank A Clock Suspend 2 Cycles Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock Preliminary 28 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 7.2. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency=2) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9 RAx CAx DQM DQHi-Z DAx0 DAx1 DAx2 DAx3 Activate Command Bank A Clock Suspend Clock Suspend 1 Cycle 2 Cycles Write Command Bank A Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock Preliminary 29 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 7.3. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency=3) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx CAx DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 Activate Command Bank A Clock Suspend Clock Suspend 1 Cycle 2 Cycles Write Command Bank A Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock Preliminary 30 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 8. Power Down Mode and Clock Mask (Burst Lenght=4, CAS# Latency=2) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE tIS tPDE Valid CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx CAx DQM tHZ Hi-Z DQ ACTIVE STANDBY Activate Read Command Command Bank A Bank A Power Down Power Down Mode Entry Mode Exit Ax0 Ax1 Ax2 Ax3 PRECHARGE STANDBY Clock Mask Start Clock Mask End Precharge Command Bank A Power Down Mode Entry Power Down Mode Exit Any Command Preliminary 31 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 9.1. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency=1) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE CS# RAS# CAS# WE# BA0,1 A10 RAw RAz A0~A9 RAw CAw CAx CAy RAz CAz DQM Hi-Z DQ Aw0 Aw1 Aw2 Aw3Ax0 Ax1 Ay0 Ay1Ay2 Ay3 Az0 Az1Az2 Az3 Activate Command Bank A Read Command Bank A Read Command Bank A Read Command Bank A Precharge Read Command Command Bank A Bank A Activate Command Bank A Preliminary 32 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 9.2. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency=2) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE CS# RAS# CAS# WE# BA0,1 A10 RAw RAz A0~A9 RAw CAw CAx CAy RAz CAz DQM DQ Hi-Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Az0 Az1 Az2 Az3 Activate Command Bank A Read Command Bank A Read Command Bank A Read Command Bank A Precharge Activate Command Command Bank A Bank A Read Command Bank A Preliminary 33 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 9.3. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency=3) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAw RAz A0~A9 RAw CAw CAx CAy RAz CAz DQM DQ Hi-Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Az0 Ay1 Ay2 Ay3 Activate Command Bank A Read Command Bank A Read Command Bank A Read Command Bank A Precharge Command Bank A Activate Command Bank A Read Command Bank A Preliminary 34 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 10.1. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency=1) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE CS# RAS# CAS# WE# BS0,1 A10 RBw RBz A0~A9 RBw CBw CBx CBy RBz CBz DQM Hi-Z DQ DBw0DBw1DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 DBz2 DBz3 Activate Command Bank A Write Command Bank B Write Command Bank A Write Command Bank B Precharge Command Bank B Activate Command Bank B Write Command Bank B Preliminary 35 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 10.2. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency=2) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RBw RBz A0~A9 RBw CBw CBx CBy RBz CBz DQM DQ Hi-Z DBw0 DBw1 Bw2 DBw3 DBx0 D DBy0 DBy1 DBx1 DBy2 DBy3 DBz0 DBz2 DBz3 DBz1 Activate Command Bank A Write Command Bank B Write Command Bank B Write Command Bank B Precharge Activate Command Command Bank B Bank B Write Command Bank B Preliminary 36 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 10.3. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency=3) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RBw RBz A0~A9 RBw CBw CBx CBy RBz CBz DQM DQ Hi-Z DBw0 DBw1DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 DBz2 Activate Command Bank A Write Command Bank B Write Command Bank B Write Command Bank B Precharge Command Bank B Activate Command Bank B Write Command Bank B Preliminary 37 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 11.1. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency=1) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE High CS# RAS# CAS# WE# BS0,1 A10 RBx RAx RBy A0~A9 RBx CBx RAx CAx RBy CBy tRCD DQM Hi-Z Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 By1 By2 tAC1 tRP DQ Activate Command Bank B Read Command Bank B Activate Command Bank A Precharge Command Bank B Activate Read Command Command Bank B Bank A Read Command Bank B Precharge Command Bank A Preliminary 38 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 11.2. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency=2) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 RBx RAx RBy A0~A9 RBx CBx RAx CAx RBy CBy tRCD DQM tAC2 tRP Hi-Z DQ Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 By1 Activate Command Bank B Read Command Bank B Activate Command Bank A Precharge Command Bank B Read Command Bank A Activate Command Bank B Read Command Bank B Preliminary 39 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 11.3. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 High CKE CS# RAS# CAS# WE# BS0,1 A10 RBx RAx RBy A0~A9 RBx CBx RAx CAx RBy CBy tRCD DQM tAC3 tRP Hi-Z DQ Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Ax7 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 By0 Activate Command Bank B Read Command Bank B Activate Command Bank A Read Command Bank A Precharge Command Bank B Activate Command Bank B Read Command Bank B Precharge Command Bank A Preliminary 40 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 12.1. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency=1) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx RBx RAy A0~A9 RAx CAx RBxCBx RAy CAy tRCD DQM tRP tWR DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DAx4 DAx5DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 Activate Command Bank A Write Command Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A Precharge Command Bank B Write Command Bank A Preliminary 41 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 12.2. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency=2) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx RBx RAy A0~A9 RAx CAx RBx CBx RAy CAy tRCD DQM tWR* tRP tWR* DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DAx4DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4DBx5 DBx6 DBx7 DAy0 DAy1DAy2 DAy3 DAy4 Activate Write Command Command Bank A Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A Write Command Bank A Precharge Command Bank B * tWR > tWR(min.) Preliminary 42 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 12.3. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency=3) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx RBx RAy A0~A9 RAx CAx RBx CBx RAy CAy tRCD DQM tWR* tRP tWR* Hi-Z DQ DAx0DAx1 DAx2 DAx3DAx4 DAx5 DAx6 DAx7 DBx0 DBx1DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 Activate Command Bank A Write Command Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A Write Command Bank A Precharge Command Bank B * tWR > tWR(min.) Preliminary 43 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 13.1. Read and Write Cycle (Burst Length=4, CAS# Latency=1) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx CAx CAy CAz DQM DQ Hi-Z Ax0 Ax1 Ax2 Ax3 DAy0DAy1 DAy3 Az0 Az1 Az3 Activate Command Bank A Read Command Bank A Read The Write Data Write Command is Masked with a Command Bank A Zero Clock Bank A Latency The Read Data is Masked with a Two Clock Latency Precharge Command Bank B Preliminary 44 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 13.2. Read and Write Cycle (Burst Length=4, CAS# Latency=2) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx CAx CAy CAz DQM DQ Hi-Z Ax0 Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Az0 Az1 Az3 Activate Command Bank A Read Command Bank A Write The Write Data Command is Masked with a Bank A Zero Clock Latency Read Command Bank A The Read Data is Masked with a Two Clock Latency Preliminary 45 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 13.3. Read and Write Cycle (Burst Length=4, CAS# Latency=3) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx CAx CAy CAz DQM DQ Hi-Z Ax0 Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Az0 Az1 Az3 Activate Command Bank A Read Command Bank A Write The Write Data Read Command is Masked with a Command Bank A Zero Clock Bank A Latency The Read Data is Masked with a Two Clock Latency Preliminary 46 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 14.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=1) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RBw A0~A9 RAx RAx RBw CBw CBx CBy CAy CBz DQM DQ Hi-Z tRCD tAC1 Ax0 Ax1 Ax2 Ax3 Bw0 Bw1 Bx0 Bx1 By0 By1 Ay0 Ay1 Bz0 Bz1 Bz2 Bz3 Activate Command Bank A Read Command Bank A Activate Command Bank B Read Command Bank B Read Command Bank B Read Command Bank B Read Command Bank A Read Command Bank B Precharge Command Bank A Precharge Command Bank B Preliminary 47 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 14.2. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RAx A0~A9 RAx CAy RAx CBw CBx CBy CAy CBz DQM tRCD tAC2 DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Bw0 Bw1 Bx0 Bx1 By0 By1 Ay0 Ay1 Bz0 Bz1 Bz2 Bz3 Activate Command Bank A Read Command Bank A Activate Command Bank B Read Read Command Command Bank B Bank B Read Command Bank B Read Command Bank A Read Command Bank B Precharge Command Bank A Precharge Command Bank B Preliminary 48 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 14.3. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE CS# RAS# CAS# WE# BS0,1 RAx RBx A10 A0~A9 RAx CAx RBx CBx CBy CBz CAy DQM Hi-Z DQ tRCD tAC3 Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 By0 By1 Bz0 Bz1 Ay0 Ay1 Ay2 Ay3 Activate Command Bank A Read Command Bank A Activate Command Bank B Read Command Bank B Read Command Bank B Read Command Bank B Read Prechaerge Command Command Bank A Bank B Precharge Command Bank A Preliminary 49 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 15.1. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=1) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RBw A0~A9 RAx CAx RBw CBw CBx CBy CAy CBz tRP DQM Hi-Z DAx0 DAx1 DAx2 DAx3 DBw0DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3 tRCD tRRD tWR tRP DQ Activate Command Bank A Activate Command Bank B Write Command Bank B Write Command Bank B Write Command Bank B Write Command Bank A Write Command Bank A Write Command Bank B Precharge Command Bank A Precharge Command Bank B Preliminary 50 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 15.2. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=2) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE CS# RAS# CAS# WE # BS0,1 A10 RAx RBw A0~A9 RAx CAx RBw CBw CBx CBy CAy CBz DQM tRCD tRRD tRP tWR tRP DQ Hi-Z DAx0 DAx1 DAx2 DAx3DBw0 DBw1 DBx0 DBx1DBy0 DBy1DAy0 DAy1 DBz0 DBz1 DBz2 DBz3 Activate Command Bank A Write Command Bank A Activate Command Bank B Write Command Bank B Write Command Bank B Write Command Bank B Write Command Bank A Write Command Bank B Precharge Command Bank A Precharge Command Bank B Preliminary 51 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 15.3. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=3) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RBw A0~A9 RAx CAx RBw CBw CBx CBy CAy CBz DQM tRCD tRRD > tRRD(min) tWR tRP tWR(min) DQ Hi-Z DAx0 DAx1 DAx2 DAx3DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3 Activate Command Bank A Activate Command Bank B Write Command Bank A Write Command Bank B Write Command Bank B Write Command Bank B Write Command Bank A Write Command Bank B Precharge Command Bank A Precharge Command Bank B Preliminary 52 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 16.1. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=1) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE High CS# RAS# CAS# WE# BS0,1 RAx RBy RBz A10 RBx A0~A9 RAx CAx RBx CBx CAy RBy CBy RBz CBz DQM DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 By0 By1 By2 By3 Bz0 Bz1 Bz2 Bz3 Activate Command Bank A Read Command Bank A Activate Command Bank B Read with Auto Precharge Command Bank B Activate Command Bank B Read with Auto Precharge Command Bank A Read with Auto Precharge Command Bank B Activate Command Bank B Read with Auto Precharge Command Bank B Preliminary 53 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 16.2. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=2) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx RBx RBy RAz A0~A9 RAx CAx RBx CBx RAy RBy CBy RAz CAz DQM Hi-Z DQ Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 By0 By1 By2 By3 Az0 Az1 Az2 Activate Command Bank A Read Command Bank A Activate Read with Command Auto Precharge Bank B Command Bank B Read with Activate Read with Activate Read with Auto Precharge Command Auto Precharge Command Auto Precharge Command Bank B Command Bank A Command Bank A Bank B Bank A Preliminary 54 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 16.3. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=3) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx RBx RBy A0~A9 RAx CAx RBx CBx CAy RBy CBy DQM DQ Hi-Z Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 By0 By1 By2 By3 Activate Command Bank A Activate Command Bank B Read Command Bank A Read with Auto Precharge Command Bank B Read with Auto Precharge Command Bank A Activate Command Bank B Read with Auto Precharge Command Bank B Preliminary 55 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 17.1. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=1) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx RBx RBy RAz A0~A9 RAx CAx RBx CBx CAy RBy CBy RAz CAz DQM Hi-Z DQ DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2DBx3 DAy0 DAy1DAy2 DAy3 DBy0 DBy1 DBy2 DBy3 DAz0 DAz0 DAz0 DAz0 Activate Command Bank A Write Command Bank A Activate Write with Command Auto Precharge Bank B Command Bank B Write with Auto Precharge Command Bank A Activate Write with Command Auto Precharge Bank B Command Bank B Activate Command Bank A Write with Auto Precharge Command Bank A Preliminary 56 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 17.2. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=2) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx RBx RBy RAz A0~A9 RAx CAx RBx CBx CAy RBy CBy RAz CAz DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DBx0 DBx1DBx2 DBx3 DAy0 DAy1DAy2 DAy3 DBy0 DBy1 DBy2 DBy3 DAz0 DAz1 DAz2 DAz3 Activate Write Command Command Bank A Bank A Activate Write with Command Auto Precharge Bank B Command Bank B Write with Auto Precharge Command Bank A Activate Write with Activate Write with Command Auto Precharge Command Auto Precharge Bank B Command Bank A Command Bank B Bank A Preliminary 57 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 17.3. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=3) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE High CS# RAS# CAS# WE# BS0,1 A9 RAx RBx RBy A0~A9 RAx CAx RBx CBx CAy RBy CBy DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 DBy0 DBy1 DBy2DBy3 Activate Command Bank A Activate Command Bank B Write Command Bank A Write with Auto Precharge Command Bank B Write with Auto Precharge Command Bank A Activate Command Bank B Write with Auto Precharge Command Bank B Preliminary 58 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 18.1. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=1) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx RBx RBy A0~A9 RAx CAx RBx CBx RBy DQM tRRD tRP Hi-Z DQ Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Bx+6 Bx+7 Activate Command Bank A Activate Command Bank B The burst counter wraps from the highest order Read page address back to zero Command during this time interval Bank A Read Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. Precharge Command Bank B Burst Stop Activate Command Command Bank B Preliminary 59 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 18.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=2) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx RBx RBy A0~A9 RAx CAx RBx CBx RBy tRP DQM Hi-Z DQ Ax Ax-2 Ax+1 Ax+2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+5 Bx+4 Bx+6 Activate Command Bank A Read Command Bank A Activate Read Precharge Full Command Command Page burst operation does not Command terminate when the burst length is satisfied; Bank B Bank B Bank B The burst counter wraps the burst counter increments and continues from the highest order bursting beginning with the starting address. page address back to zero Burst Stop during this time interval Command Activate Command Bank B Preliminary 60 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 18.3. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=3) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx RBx RBy A0~A9 RAx CAx RBx CBx RBy DQM tRP DQ Hi-Z Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Activate Command Bank A Read Command Bank A Activate Command Bank B Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval Precharge Full Page burst operation does not Command terminate when the burst length is Bank B satisfied; the burst counter increments and continues bursting beginning with the Burst Stop starting address. Command Activate Command Bank B Preliminary 61 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 19.1. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=1) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx RBx RBy A0~A9 DQM RAx CAx RBx CBx RBy DQ Hi-Z DBx DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+ 1 DBx+1 DBx+ 2 DBx+ 3 DBx+4 DBx+5 DBx+6 DBx+7 Activate Command Bank A Activate Command Bank B The burst counter wraps from the highest order Write page address back to zero Command during this time interval Bank A Write Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. Data is ignored Precharge Command Bank B Burst Stop Activate Command Command Bank B Preliminary 62 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 19.2. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=2) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx RBx RBy A0~A9 RAx CAx RBx CBx RBy DQM DQ Hi-Z DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx-1 DAx DAx+ 1 DBx DBx+1DBx+ 2 DBx+ 3 DBx+4 DBx+5 DBx+6 Activate Command Bank A Write Command Bank A Write Activate Command Command Bank B Bank B The burst counter wraps Full Page burst operation does not terminate when the burst from the highest order page address back to zero length is satisfied; the burst counter increments and continues bursting during this time interval beginning with the starting address. Data is ignored Precharge Command Bank B Burst Stop Command Activate Command Bank B Preliminary 63 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 19.3. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=3) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx RBx RBy A0~A9 RAx CAx RBx CBx RBy DQM Data is ignored DQ Hi-Z DBx DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx-1 DAx DAx+ 1 DBx+1 DBx+ 2 DBx+ 3 DBx+4 DBx+5 Activate Command Bank A Write Command Bank A Activate Write Command Command Bank B Bank B The burst counter wraps Full Page burst operation does from the highest order page address back to zero not terminate when the burst length is satisfied; the burst counter during this time interval increments and continues bursting beginning with the starting address. Precharge Command Bank B Burst Stop Command Activate Command Bank B Preliminary 64 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 20. Byte Write Operation (Burst Length=4, CAS# Latency=2) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx CAx CAy CAz LDQM UDQM DQ0 - DQ7 Ax0 Ax1 Ax2 DAy2 DAy1 Az1 Az2 DQ8 - DQ15 Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Az0 Az1 Az2 Az3 Activate Command Bank A Upper 3 Bytes Read are Command masked Bank A Lower Byte is masked Write Upper 3 Bytes Read Command are masked Command Bank A Bank A Lower Byte is masked Lower Byte is masked Preliminary 65 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 21. Random Row Read (Interleaving Banks) (Burst Length=2, CAS# Latency=1) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE High Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A CS# RAS# CAS# WE# BS0,1 A10 RBu RAu RBv RAv RBw RAw RBx RAx RBy RAy RBz RAz A0~A9 RBu CBu RAu CAu RBv CBv RAv CAv RBw CBw RAw CAw RBx CBx RAx CAx RBy CBy RAy CAy RBz CBz RAz DQM tRP tRP tRP tRP t RP tRP t RP tRP tRP tRP DQ Activate Command Bank B Bu0 Bu1 Au0 Au1 Bv0 Bv1 Av0 Av1 Bw0 Bw1 Aw0 Aw1Bx0 Bx1 Ax0 Ax1 By0 By1 Ay0 Ay1 Bz0 Activate Command Bank A Activate Command Bank B Activate Command Bank A Activate Command Bank B Activate Command Bank A Activate Command Bank B Activate Command Bank A Activate Command Bank B Activate Command Bank A Activate Command Bank B Activate Command Bank A Read Bank B with Auto Precharge Read Bank A with Auto Precharge Read Bank B with Auto Precharge Read Bank A with Auto Precharge Read Bank B with Auto Precharge Read Bank A with Auto Precharge Read Bank B with Auto Precharge Read Bank A with Auto Precharge Read Bank B with Auto Precharge Read Bank A with Auto Precharge Read Bank B with Auto Precharge Preliminary 66 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 22. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RBx RBw A0~A9 RAx RBx CAx CBx CAy CBy CAz CBz RBw tRP DQM tRRD DQ tRCD Ax0 Bx0 Ay0 Ay1 By0 By1 Az0 Az1 Az2 Bz0 Bz1 Bz2 Activate Command Bank A Activate Command Bank B Read Read Command Command Bank B Read Bank B Command Read Bank A Command Bank A Read Command Bank A Read Command Bank B Precharge Command Bank B (Precharge Temination) Activate Command Bank B Preliminary 67 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 23. Full Page Random Column Write (Burst Length=Full Page, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RBx RBw A0~A9 RAx RBx CAx CBx CAy CBy CAz CBz RBw tWR DQM tRP tRRD DQ tRCD DAx0DBx0DAy0 DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 DBz1 DBz2 Activate Command Bank A Activate Command Bank B Write Command Bank B Write Write Command Command Bank A Bank A Write Command Bank B Write Command Bank A Write Command Bank B Precharge Command Bank B (Precharge Temination) Activate Write Data Command Bank B is masked Preliminary 68 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 24.1. Precharge Termination of a Burst (Burst Length=Full Page, CAS# Latency=1) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK1 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RAy RAz CAy A0~A9 RAx CAx RAy RAz CAz tWR tRP DQM tRP Precharge Termination of a Read Burst. DQ DAx0 DAx1 DAx2 DAx3 DAx4 Ay0 Ay1 Ay2 DAz0 DAz1 DAz2 DAz3 DAz4 DAz5 DAz6 DAz7 Read Activate Precharge Termination Precharge Command Command Command of a Write Burst. Bank A Bank A Write data is masked. Bank A Write Activate Command Command Bank A Bank A Precharge Command Bank A Write Command Bank A Activate Command Bank A Preliminary 69 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 24.2. Precharge Termination of a Burst (Burst Length=8 or Full Page, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx RAy RAz A0~A9 RAx CAx RAy CAy RAz CAz tWR tRP DQM tRP tRP DQ DAx0 DAx1 DAx2 DAx3 Ay0 Ay1 Ay2 Az0 Az1 Az2 Activate Command Bank A Write Precharge Command Command Bank A Bank A Precharge Termination of a Write Burst. Write data is masked. Activate Command Bank A Read Command Bank A Precharge Command Bank A Activate Command Bank A Precharge Read Command Command Bank A Bank A Precharge Termination of a Read Burst Preliminary 70 Rev 1.4 Oct. 2005 EtronTech 2Mega x 32 SDRAM EM638325 Figure 24.3. Precharge Termination of a Burst (Burst Length=4, 8 or Full Page, CAS# Latency=3) T0 CLK T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx RAy RAz A0~A9 RAx CAx RAy CAy RAz tWR DQM tRP tRP DQ DAx0 DAx1 Ay0 Ay1 Ay2 Activate Command Bank A Write Command Bank A Write Data is masked Precharge Command Bank A Activate Command Bank A Read Command Bank A Precharge Command Bank A Activate Precharge Termination Command of a Read Burst Bank A Precharge Termination of a Write Burst Preliminary 71 Rev 1.4 Oct. 2005 EtronTech 86 2Mega x 32 SDRAM EM638325 86 Pin TSOP II Package Outline Drawing Information 44 HE E 0.254 L L1 1 D 43 A1 A2 A e S B y L L1 Symbol A A1 A2 B C D E e HE L L1 S y Dimension in inch Min Normal Max 0.047 0.002 0.004 0.006 0.037 0.039 0.041 0.007 0.008 0.009 0.005 0.87 0.875 0.88 0.395 0.400 0.405 0.0197 0.455 0.463 0.471 0.016 0.020 0.024 0.0315 0.024 0.004 8 0 Min 0.05 0.95 0.17 22.09 10.03 11.56 0.40 0 Dimension in mm Normal 0.10 1 0.2 0.127 22.22 10.16 0.50 11.76 0.50 0.80 0.61 Max 1.20 0.15 1.05 0.23 22.35 10.29 11.96 0.60 0.10 8 Notes : 1. Dimension D&E do not include interiead flash. 2. Dimension B does not include dambar protrusion/intrusion. 3. Dimension S includes end flash. 4. Controlling dimension : mm Preliminary 72 Rev 1.4 Oct. 2005 C |
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